An Analytical Model for On-Chip Interconnects in Multimedia Embedded Systems
Wu, Y. ; Min, Geyong ; Zhu, D. ; Yang, L.T.
Wu, Y.
Min, Geyong
Zhu, D.
Yang, L.T.
Publication Date
2013
End of Embargo
Supervisor
Rights
Peer-Reviewed
Yes
Open Access status
Accepted for publication
Institution
Department
Awarded
Embargo end date
Additional title
Abstract
The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects. Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection network under bursty multimedia traffic and nonuniform message destinations. Extensive simulation experiments are conducted to validate the accuracy of the model, which is then adopted as a cost-efficient tool to investigate the effects of bursty multimedia traffic with nonuniform destinations on the network performance.
Version
No full-text available in the repository
Citation
Wu Y, Min G, Zhu D et al (2013) An analytical model for on-chip interconnects in multimedia embedded systems. ACM Transactions on Embedded Computing Systems. 13(1S): Article 29.
Link to publisher’s version
Link to published version
Link to Version of Record
Type
Article