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dc.contributor.authorTatas, K.*
dc.contributor.authorSiozios, K.*
dc.contributor.authorBartzas, A.*
dc.contributor.authorKyriacou, Costas*
dc.contributor.authorSoudris, D.*
dc.date.accessioned2016-10-07T14:39:17Z
dc.date.available2016-10-07T14:39:17Z
dc.date.issued2013
dc.identifier.citationTatas K, Siozios K, Bartzas A, Kyriacou C et al (2013) A novel prototyping and evaluation framework for NoC-based MPSoC. International Journal of Adaptive, Resilient and Autonomic Systems. 4(3): 1-24.
dc.identifier.urihttp://hdl.handle.net/10454/9739
dc.descriptionNo
dc.description.abstractThis paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.
dc.subjectMPSoC; Register Transfer-Level; RTL; Network-on-Chip; NoC; Non-Recurring Engineering; NRE
dc.titleA Novel Prototyping and Evaluation Framework for NoC-Based MPSoC
dc.status.refereedYes
dc.typeArticle
dc.type.versionNo full-text available in the repository
dc.identifier.doihttps://doi.org/10.4018/jaras.2013070101


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