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dc.contributor.authorGhani, A.*
dc.contributor.authorSee, Chan H.*
dc.contributor.authorMigdadi, Hassan S.O.*
dc.contributor.authorAsif, Rameez*
dc.contributor.authorAbd-Alhameed, Raed A.*
dc.contributor.authorNoras, James M.*
dc.date.accessioned2016-09-21T15:38:58Z
dc.date.available2016-09-21T15:38:58Z
dc.date.issued2015
dc.identifier.citationGhani A, See CH, Migdadi HSO et al (2015) Reconfigurable neurons - making the most of configurable logic blocks (CLBs). In Internet Technologies and Applications (ITA) 8-11 Sep 2015. Wrexham, UK: 475-478.
dc.identifier.urihttp://hdl.handle.net/10454/9152
dc.descriptionNo
dc.description.abstractAn area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.
dc.relation.isreferencedbyhttp://dx.doi.org/10.1109/ITechA.2015.7317451
dc.subjectNeural signal processing; Recurrent neural networks; Reservoir computing; Reconfigurable computing; FPGAs
dc.titleReconfigurable neurons - making the most of configurable logic blocks (CLBs)
dc.status.refereedYes
dc.typeConference Paper
dc.type.versionNo full-text available in the repository


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