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dc.contributor.advisorNot named
dc.contributor.authorLogan, Nandi*
dc.date.accessioned2011-11-09T17:51:28Z
dc.date.available2011-11-09T17:51:28Z
dc.date.issued2010
dc.identifier.urihttp://hdl.handle.net/10454/5188
dc.description.abstractSilicon CMOS Technology is now the preferred process for low power wireless communication devices, although currently much noisier and slower than comparable processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing gate sizes and correspondingly higher speeds, higher Ft CMOS processes are increasingly competitive, especially in low power wireless systems such as Bluetooth, Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS technology, but at a reduced operational voltage, even with thicker gate oxides as compensation. This thesis investigates newer techniques, both from a systems point of view and at a circuit level, to implement an efficient transceiver design that will produce a more sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a starting point, the overall components and available SoC were investigated, together with their architecture. Two novel techniques were developed during this investigation. The first was a high compression point LNA design giving a lower overall systems noise figure for the receiver. The second was an innovative means of matching circuits with low Q components, which enabled the use of smaller inductors and reduced the attenuation loss of the components, the resulting smaller circuit die size leading to smaller and lower cost commercial radio equipment. Both these techniques have had patents filed by the University. Finally, the overall design was laid out for fabrication, taking into account package constraints and bond-wire effects and other parasitic EMC effects.en_US
dc.language.isoenen_US
dc.rights<a rel="license" href="http://creativecommons.org/licenses/by-nc-nd/3.0/"><img alt="Creative Commons License" style="border-width:0" src="http://i.creativecommons.org/l/by-nc-nd/3.0/88x31.png" /></a><br />The University of Bradford theses are licenced under a <a rel="license" href="http://creativecommons.org/licenses/by-nc-nd/3.0/">Creative Commons Licence</a>.en_US
dc.subjectRF Receiversen_US
dc.subjectInductorsen_US
dc.subjectNoise Figureen_US
dc.subjectComponent Quality Factoren_US
dc.subjectCMOSen_US
dc.subjectSensitivityen_US
dc.subjectCompression Pointen_US
dc.subjectLNAen_US
dc.subjectUMTSen_US
dc.titleCMOS design enhancement techniques for RF receivers. Analysis, design and implementation of RF receivers with component enhancement and component reduction for improved sensitivity and reduced cost, using CMOS technology.en_US
dc.type.qualificationleveldoctoralen_US
dc.publisher.institutionUniversity of Bradfordeng
dc.publisher.departmentSchool of Engineering, Design and Technologyen_US
dc.typeThesiseng
dc.type.qualificationnamePhDen_US
dc.date.awarded2010
refterms.dateFOA2018-07-19T07:50:16Z


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