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dc.contributor.authorShepherd, Simon J.*
dc.contributor.authorNoras, James M.*
dc.contributor.authorZhou, Yuan*
dc.date.accessioned2009-07-27T12:05:52Z
dc.date.available2009-07-27T12:05:52Z
dc.date.issued2007
dc.identifier.citationZhou Y, Noras JH and Shepherd SJ (2007) Novel design of multiplier-less FFT processors. Signal Processing. 87(6): 1402-1407.en
dc.identifier.urihttp://hdl.handle.net/10454/3129
dc.descriptionNoen
dc.description.abstractThis paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.en
dc.language.isoenen
dc.subjectFFTen
dc.subjectSystolic arrayen
dc.subjectCSDen
dc.subjectPhase-amplitude splittingen
dc.subjectMultiplier-less architectureen
dc.titleNovel design of multiplier-less FFT processorsen
dc.status.refereedYesen
dc.typeArticleen
dc.type.versionNo full-text in the repositoryen
dc.identifier.doihttps://doi.org/10.1016/j.sigpro.2006.12.004


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