Publication

Novel design of multiplier-less FFT processors

Shepherd, Simon J.
; 
Noras, James M.
; 
Zhou, Yuan
Publication Date
2007
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Keywords
FFT, Systolic array, CSD, Phase-amplitude splitting, Multiplier-less architecture
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Peer-Reviewed
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closedAccess
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Engineering and Digital Technology Publications
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Abstract
This paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.
URI
http://hdl.handle.net/10454/3129
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Citation
Zhou Y, Noras JH and Shepherd SJ (2007) Novel design of multiplier-less FFT processors. Signal Processing. 87(6): 1402-1407.
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Link to Version of Record
https://doi.org/10.1016/j.sigpro.2006.12.004
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Article
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