A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC
Tatas, K. Siozios, K. Bartzas, A. Kyriacou, Costas Soudris, D.
Tatas, K.
Siozios, K.
Bartzas, A.
Kyriacou, Costas
Soudris, D.
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2013
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Abstract
This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.
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Tatas K, Siozios K, Bartzas A, Kyriacou C et al (2013) A novel prototyping and evaluation framework for NoC-based MPSoC. International Journal of Adaptive, Resilient and Autonomic Systems. 4(3): 1-24.
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